June 2, 2025

Intel and SoftBank collaborate on power-efficient HBM substitute for AI data centers, says report

American chip giant Intel has partnered with Japanese tech and investment powerhouse SoftBank to build a stacked DRAM substitute for HBM. According to Nikkei Asia, the two industry behemoths set up Saimemory to build a prototype based on Intel technology and patents from Japanese academia, including the University of Tokyo.
May 28, 2025

TSMC reiterates it doesn’t need High-NA EUV for 1.4nm-class process technology

TSMC reiterated its long-known stance on next-generation High-NA EUV lithography tools at its European Technology Symposium in Amsterdam. The company does not require these highest-end lithography systems for its next-generation process technologies, including A16 (1.6nm-class) and A14 (1.4nm-class) process technologies.
May 6, 2025

Intel officially cuts Core Ultra 7 200-series desktop CPU prices by up to 25%

On Tuesday, Intel notified Tom's Hardware that it officially cut the suggested retail price (SRPs) of its boxed Core Ultra 7 200-series processors for desktops by around $100. It is common for CPU developers to cut the prices of their products, but it is uncommon for companies like Intel to formally confirm such moves. However, there is a small catch: since we are dealing with SRPs, actual prices may vary.
April 21, 2025

AMD 16-core Zen 5c die shots show long, narrow CCX, all 16 cores sharing a single L3 cache

Die shots of AMD's 16-core Zen 5c CCD used in its latest EPYC 9005 series server processors have been exposed, revealing clear differences compared to AMD's previous-generation Zen 4c CCDs. Posted by HXL on X, photos of AMD's 16-core 3nm Zen 5c CCD expose a long row of two banks of cores flanking a 32MB layer of L3 cache in the middle of the die.